The present invention relates generally to the field of communication devices. More specifically, the present invention is related to high capacity computer-based telecommunication devices.
As computer telephony becomes an integral part of the existing communications network, including the Internet, there are increasing challenges in making diverse communication products work together. One of the elements in the development of computer-based communications has been the incorporation of auxiliary telecom busses to existing computer systems. These busses are incorporated into high capacity computer-based telecommunications equipment and typically transport Nxc3x9764 Kbps low-latency communications traffic between the cards of the system, independently from the computer""s I/O and memory busses. One such bus is defined by the Enterprise Computer Telephony Forum and is designated as H.110. H.110 is a TDM based bus providing up to 4096 time slots at 8 MHz for voice and/or data communications. This bus has been targeted to CompactPCI (cPCI) form factor products. The incorporation of this bus into the computer systems meeting the cPCI specification has been met with some problems in the art as will be discussed below.
CompactPCI is a standard laid forth by the PCI Industrial Manufacturers Group (PICMG) which specifies an electrical superset of desktop PCI utilizing a form factor suitable for rugged applications (e.g. industrial computers). The form factor of cPCI is based upon the Eurocard form factor popularized by the VME bus. CompactPCI utilizes 2 mm metric pin and socket connectors with cPCI cards inserted from the front of the chassis with I/O breakout either to the front or rear.
The form factor for cPCI cards is illustrated in FIG. 1. CompactPCI standard supports both 3U 100 (100 mm by 160 mm) and 6U 102 (233.35 mm by 160 mm) card sizes. The rear card connectors are designated J1-J5 (or P1-P5) 104-112, in the PICMG specification, starting from the bottom of the card. 3U 100 cPCI cards utilize both J1104 and J2106 providing 220 pins for power, ground and all 32 bit and 64 bit PCI signals. The J1104 (or P1) is 110 pins and the J2106 (or P2) is 110 pins. The card connectors are female connectors and the backplane connectors are male connectors. The 3U form factor is the minimum for cPCI supporting 64 bit transfers, however, cards which are to only perform 32 bit transfers can utilize only the lower connector J1104. 6U 102 extensions are defined for cards where extra card area or connection space is needed. The use of the remaining connectors J3108, J4110, and J5112 are designated in the specification as capable of being user designed for specific applications.
A cPCI system is composed of one or more cPCI bus segments. Each segment comprises up to eight (eight being the limitation due to electrical load considerations) card locations at 33 MHz. A typical cPCI backplane utilizing a single cPCI segment 200 is illustrated in FIG. 2. The cPCI backplane comprises the male J1202 and J2204 (only numbered for slot 8206 for clarity) connectors for each of the card locations/slots 206-220. Each cPCI segment comprises a system slot 220 and up to seven peripheral slots 206-218. The system slot card (system card) provides arbitration, clock distribution and reset functions for the other cards on the segment. The system slot card is also manages each local card""s IDSEL signal in order to perform system initialization.
At times, a cPCI system needs to utilize more than eight slots. The PICMG defines a means for cPCI system cards to drive two independent PCI bus segments in a 6U environment. This is illustrated in FIG. 3. System card 300 is constructed to the 6U form factor with the first PCI segment/bus connected to connectors J1302 and J2304. The second PCI segment/bus is connected to the card via connectors J4306 and J5308. The first bus is referred to the PCI bus A or PCI bus B while the second bus is designated as the PCI bus C. System card 300 utilizes PCI bridge chips 310, 312 and an on card PCI bus to bridge between the first segment and the second segment.
Purportedly, one of the advantages to implementing a system utilizing a 6U form factor is to support extra features for an industrial system. For instance the industrial computer system is designed for computer telephony applications. In these instances, a provision must be made for a telecom bus for the transport and switching of telecom data streams between the cards in the chassis. Two important specifications related to the implementation of a telecom bus in a cPCI chassis are the PICMG 2.5 Computer Telephony specification and the ECTF H.110 (CT) bus specifications. The specifications make use of the J4 connector and, therefore, the J4 connector is a precious connector for telecommunication equipment manufacturers. The PICMG architecture for bridging between two PCI segments creates a wasteful use of the J4/J5 connectors and further prevents the addition of a second telecom bus such as the H.110.
There is an additional need for a high capacity computer-based telecommunications device which can support a number of communication protocols. The system architecture of the present invention allows for the creation of a high capacity computer-based device which can handle a number of communication protocols. As previously noted, the Internet, or IP based networks in general, have become an important part of the current communications infrastructure. In a further embodiment, the present invention""s unique architecture is utilized to provide a device which combines traditional IP routing capabilities with a gateway for non-IP traffic to the IP network. When the high capacity computer-based telecommunications device based upon the system architecture is used as a gateway, there are difficulties associated with the routing of the data, as will be described below.
The IP routing means that the device can receive IP datagrams from one IP network and forward it to the correct destination, according to the destination IP address within the datagram. When working as a gateway, a voice gateway for example, the device uses its own IP address to represent the non-IP voice channels on the IP network. To separate the incoming IP datagrams to their specific voice channel, there""s a need to identify each voice flow. Since all those flows use the device IP as destination address, there""s a need to look at higher layer parameters to identify a flow. Voice streams, for example, use TCP and RTP as transport layers. Each voice flow is identified by a unique  less than source IP, source UDP port, destination IP, destination UDP port greater than combination.
The handling of IP routing involves mapping of the 32 bits of the IP address to a correct destination (traditional routing operation). Since there are 232 different IP address, it""s not practical to use a lookup table that stores the destination information, where the IP address is the entry index to this lookup table. In order to solve this mapping problem, there""s a need to employ more sophisticated hashing and caching algorithms. The problem is further complicated when dealing with locally designated IP data flows (flows whose destination IP address is the local IP address of the device). These are used when the device is working as a gateway from IP to non-IP traffic.
Traditional IP routing typically involves routing only at layer 3 (by mapping the IP address as described above). A traditional router does not look at the layer 4 and above protocols to determine a destination. Datagrams are simply encapsulated in a MAC frame and forwarded to the destination device. It is the responsibility of the layer 4 and above protocols at the destination device to properly identify the unique flow (typically based upon the IP destination and source address and the TCP/UDP source and destination address). This requires additional overhead on the destination device""s layer 4 and above software/hardware, as it has to decode the layer 3, 4 and above headers in order to identify the data flow.
Due to the fact that IP data is packet based, busses which follow packet based standards are advantageous to utilize in the transmission of IP datagrams. One such set is so called LANs based upon IEEE 802 standards. For these xe2x80x9cnetwork bussesxe2x80x9d, the IEEE 802 standards specify the layer 1 and layer 2 protocols. One of the most commonly utilized standards is the IEEE 802.3 (Ethernet and Fast Ethernet), and more recently the IEEE 802.3 z (Gigabit Ethernet), all based upon a CSMA/CD medium access control technique.
These busses may be arranged in a number of topologies. One such topology is the star topology. In the star topology, each device connected to the bus is connected directly to a common central node utilizing point-to-point connections. Other commonly utilized topologies include bus, tree, and ring.
The system architecture of the present invention provides a solution to the problems, along with additional advantages, which will be obvious to one of skill in the art from the detailed description, drawings and appended claims.
The backplane of the present invention is an enhance backplane supporting a plurality of busses working independently of each other and each utilized for a different data type. The backplane supports at least one peripheral connection bus (I/O bus), at least one telecom bus, and at least one network bus. The system provides for the scalability of the peripheral connection bus through bridging between two peripheral connection busses. A first serializer, operatively connected to the first peripheral bus, is used to receive data from a first peripheral connection bus, serializes the data, and transfers the serial data stream to a second serializer which is operatively coupled to the second bus. The second serializer de-serializes the transferred data and transfers it to the second peripheral connection bus.
The backplane is utilized with a router and I/O cards to provide a device which combines traditional IP routing capabilities with a gateway for non-IP traffic to the IP network. A unique routing method is utilized to reduce the overhead associated with identifying data flows at the I/O card. The router receives the incoming datagrams and looks at the layer 3 and above headers to determine which I/O card to send the data to and to identify the data flow. The router then encapsulates the data into a specialized frame which designates the I/O card and uniquely identifies the data flow and forwards this over the network bus to the appropriate card. The card then determines the destination of the data via the specialized frame without having to look at the layer 3 and above headers.